1. Field of the Invention
The present invention relates to the manufacturing of semiconductor integrated circuits and more specifically to the final steps of this manufacturing during which are formed, above a silicon substrate including diffused regions and selected structures, a succession of insulating layers alternating with metal layers. Each of the metal layers forms a metallization level. Each metallization level is etched according to a determined topology to establish contacts with vias connecting this metal layer to a lower metal layer and to an upper metal layer. The highest layer is connected to contact pads and the lowest layer is connected by vias to portions of the semiconductor substrate and/or to polysilicon regions.
2. Discussion of the Related Art
Successive problems of via formation within a dielectric layer, of dielectric layer etching and of metal layer etching are thus raised. Various methods have been developed in the art to form such interconnection layers and these methods are now well tried and tested with conventional materials such as silicon oxide and aluminum.
However, as technical developments lead to reducing the sizes of elementary components in the silicon, the sizes of the patterns formed in the various metallization layers are similarly reduced and the metallizations are brought closer to one another. This results, in particular, in an increase of vertical stray capacitances between metal layers of different levels and of lateral stray capacitances between portions of metallizations of the same level. To avoid increasing the value of the stray capacitances, which reduces the maximum circuit switching rate, dielectrics having smaller dielectric constants than that of silicon oxide are desired to be used. However, a common disadvantage of many of these dielectrics is that they are difficult to etch.
It has also been attempted to use conductive materials more conductive than aluminum, such as copper. Again, with such elements, great difficulties arise to etch these materials in a localized way, for example to form trenches with steep sides or to electrically insulate the patterns from one another.
These problems have been solved, especially by the techniques described in U.S. patent application Ser. No. 09/196,851, which in incorporated herein by reference, which also describes various known methods of interconnection structure formation.
To further reduce lateral stray capacitances between portions of metallizations of the same level, it has been suggested to perform insulator depositions so that there remains a void (an air bubble) between neighboring metallization portions of the same level. Porous insulator depositions have also been provided. This raises new problems that the present invention aims at solving.
Thus, an object of the present invention is to provide a novel method of implementing structures including several conductive levels separated by insulating layers locally crossed by vias filled with metal.
Another object of the present invention is to provide such a method in which pores or voids are made between neighboring metallizations of a same level.
To achieve these and other objects as well as others, the present invention provides a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended to be contacted by a via crossing the second insulating layer.
According to an embodiment of the present invention, the metal areas are copper, silver, or gold areas, or are made of several alloys of copper with materials selected from the group including aluminum, silicon, manganese, and cobalt.
According to an embodiment of the present invention, the second insulating layer, non-conformally deposited so that gaps can form, is made of a material selected from the group including silicon oxide, and fluorine- or carbon-doped silicon oxides, deposited by chemical vapor deposition.
According to an embodiment of the present invention, the second insulating layer, intended for providing a porous layer, is an aerogel or a xerogel.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.